Various techniques have been investigated and used for metallizing semiconductor chips. These methods include the lift-off process, thru-mask methods, metal RIE and metal and insulator damascene and various combinations of the above-methods. The lift-off and thru-mask methods are more valuable for large features, like those typically encountered in chip packaging. Unlike the lift-off and the thru-mask, the metal RIE and damascene methods have been the process of choice for chip metallizations where the ground rules are typically below one micron.
In the damascene process, metal film is deposited over the entire patterned substrate surfaces to fill trenches and vias. This is then followed by metal planarization to remove metal overburden and isolate and define the wiring pattern. When metal deposition is by electroplating or by electroless process, the plating is preceded by the deposition of a plating base or seedlayer over the entire surface of the patterned wafer or substrate. Also, layers that may improve adhesion, and prevent conductor/insulator interactions or interdiffusion are deposited between the plating base or seedlayer and the insulator.
In the metal RIE methods, blanket metal film is etched to define the conductor pattern. The gaps between the metal lines and vias are then filled with insulators. In high performance applications, the dielectric is planarized to define a flat metal level. One of the main advantages of the damascene process as compared to metal RIE is that it is often easier to etch an insulator as opposed to metal. Also, insulator gap fill and planarization may be more problematic.
In the metal damascene process, all the recesses in the insulator are first filled with metal before metal polishing. However, during the metal deposition into trenches and vias, all the narrower features become filled before their wider counterparts. Thus, all features with widths less than 2 microns will be filled before those with widths greater than 5 microns. Hence, to fill trenches or test pads with widths of 50 microns, the smaller recesses typically with widths less than 5 microns are overplated. During metal CMP, the additional time needed to remove the excess metal overburden on the overplated smaller features causes dishing on the larger features. Also, because of the prolonged polishing times, insulator adjacent may become severely eroded. Severe dishing and insulator erosion in large metal features is a source of yield loss, especially when the occur at lower levels. Here they cause trapped metal defects at the next higher level. The longer time needed to remove the thicker metal overburden on the smallest metal lines and vias is one of the main culprits responsible for the low thruput and yield losses in the metal CMP process.
Moreover, this last metal wiring level typically contains very wide metal lines for power bussing and large pads for wirebonds or C4 solder balls. In the CMP process, these relatively large metal structures are sensitive to dishing because of the prolonged polishing times. Accordingly, room exists for improving the metal deposition process.